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Pull requests: llvm/circt

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Pull requests list

Bump slang 11.0
#10488 opened May 16, 2026 by mi-and-core Loading…
[Synth] add synth.mux_inv
#10486 opened May 16, 2026 by okekayode Contributor Loading…
4
[OM][firtool][om-linker] Elaborate public classes before emission/after linking.
#10480 opened May 16, 2026 by uenoku Member Loading…
1
[SV] Add pass to hide non-synthesizable ops SV System Verilog Dialect
#10479 opened May 15, 2026 by teqdruid Contributor Loading…
1
2
[ImportVerilog] Preserve declaration order across regular and interface-modport ports
#10468 opened May 14, 2026 by micprog Contributor Loading…
1
[ImportVerilog] Add support for oneshot
#10465 opened May 14, 2026 by jpienaar Member Loading…
1
ci: declare minimum permissions on dispatchCirctTests workflow
#10462 opened May 14, 2026 by arpitjain099 Contributor Loading…
[Draft][Moore][ImportVerilog][MooreToCore][Sim] Add file I/O system tasks support.
#10460 opened May 14, 2026 by VecoMr • Draft
16
[LowerToHW] Add support for lower-to-core in firrtl.fprintf
#10452 opened May 13, 2026 by nanjo712 Contributor Loading…
5
[HW] Add forceable wire support with HW RefType
#10447 opened May 12, 2026 by prithayan Contributor • Draft
[DRAFT][FIRRTLToHW] Emit sim.proc.print instead of sim.print
#10441 opened May 12, 2026 by nanjo712 Contributor • Draft
[OM] Support evaluated object evaluator flow
#10440 opened May 12, 2026 by uenoku Member Loading…
3
Add results to sv.ifdef
#10436 opened May 12, 2026 by prithayan Contributor • Draft
2
[Sim] Extract common logic of ProceduralizeSim for reuse
#10422 opened May 9, 2026 by nanjo712 Contributor Loading…
6
[FIRRTL] Add mux2cell/mux4cell canonicalization patterns
#10414 opened May 8, 2026 by anaumchev Loading…
2
1
[debug][firrtl] Carry Chisel source-level types through the pipeline
#10410 opened May 7, 2026 by fkhaidari Loading…
[HW] HWVectorization Part 4: Partial Vectorization (Chunking)
#10399 opened May 6, 2026 by mafeguimaraes Contributor Loading…
[CI] Enable macos wheel building
#10371 opened May 1, 2026 by jumerckx Loading…
13
[Support] Add parallel instance graph visitors
#10353 opened Apr 29, 2026 by seldridge Member • Draft
4
[ImportVerilog] Support use-before-declare across module bodies
#10350 opened Apr 28, 2026 by AmurG Contributor Loading…
6
[FIRRTL] LowerLayers: Inline enabled layers FIRRTL Involving the `firrtl` dialect
#10348 opened Apr 28, 2026 by rwy7 Contributor Loading…
4
[ImportVerilog] HierarchicalNames should skip reprocessing identical module instances
#10341 opened Apr 28, 2026 by rocallahan Contributor • Draft
8
fix: update flattenIndices to generate correct indices for a flattened memref
#10327 opened Apr 25, 2026 by Abhilekhgautam Loading…
1
6
[FIRRTL] Eliminate Implicit Truncation
#10294 opened Apr 21, 2026 by darthscsi Contributor Loading…
17
[OM] Introduce explicit evaluator state and op patterns
#10265 opened Apr 18, 2026 by uenoku Member • Draft
1
14
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